In general, since a CMOS inverter has a structure in which an NMOS transistor and a PMOS transistor are neighboring to each other, there occurs a latch up problem. The latch up increases power consumption of an entire chip in geometrical progression, resulting in inducing malfunction and destruction of the chip.
Hereinafter, with reference to a diagram of a general CMOS inverter, there will be explained a latch up phenomenon occurring in a CMOS region.
Referring to FIG. 1, there is shown a cross-sectional view of an NMOS and a PMOS transistor constructing a CMOS inverter.
The CMOS inverter is made with a P type substrate 101. An N-well 102 is formed on the P type substrate 101 and, in order to make the PMOS transistor within the N-well 102, there are formed p+ impurity diffusion regions 103a and 103b, which are a source and a drain of the PMOS transistor. In order to pick up the N-well 102, there is formed an n+ impurity diffusion region 104. Furthermore, a P-well 105 is constructed on an N type substrate and, in order to make the NMOS transistor within the P-well 105, there are formed n+ impurity diffusion regions 106a and 106b. To pick up the P-well 105, there is made a p+ impurity diffusion region 107. In this structure, the CMOS inverter contains a PNP type bipolar junction transistor 108 in the PMOS area and an NPN type bipolar junction transistor 109 in the NMOS area as two undesired parasitic bipolar junction transistors when the chip operates.
Since there is generated a path of low resistance between Vdd and Vss as the two parasitic bipolar junction transistors 108 and 109 interact, excess current flows from Vdd to Vss and, as a result, there occurs the latch up phenomenon which induces the destruction and malfunction of a device.
FIGS. 2A and 2B provide energy band diagrams of an NMOS transistor.
As shown in FIG. 2A, if a voltage is not provided to a gate electrode, since a structure of source-channel-drain about beneath an insulating layer of a gate is an N-P-N junction structure, the channel region at a center acts as a barrier to block electron flow between the source and the drain. However, as described in FIG. 2B, if a positive voltage is sufficiently supplied to the gate electrode, since a gate voltage becomes higher than a threshold voltage Vth and, thus, an energy band of the channel region moves to a lower level by a junction field effect, a barrier of the channel region lowers enough and, as a result, electrons can flow between the source and the drain. That is, if the source-channel-drain has an N-N-N structure, the channel type is changed from P to N or from N to P and this kind of phenomenon is called by carrier inversion. As can be seen above, in a MOS field effect transistor (MOSFET), the channel between the source and the drain can be turned on or off by adjusting the gate voltage.
A bipolar junction transistor also operates like the MOSFET described above.
FIGS. 3A to 3C describe energy band diagrams of a PNP type bipolar junction transistor.
FIG. 3A shows a condition that a voltage is not supplied to each node of an emitter, a base and a collector of the transistor. The base region at a center acts as a barrier to block electron flow between the emitter and the collector. If a forward voltage is provided to between the emitter and the base or between the collector and the base, since an energy level of the base rises and, thus, a PN diode is turn on, there occurs current flow in the bipolar junction transistor. As described in FIG. 3B, since a supply voltage Vdd is provided to the emitter electrode in a practical operation, when the base electrode is provided by a voltage Vpp which is boosted as much as a minimum threshold voltage Vth from the supply voltage Vdd in a semiconductor circuit and the collector electrode is supplied by a voltage Vbb which is reduced as much as the minimum threshold voltage Vth from a ground voltage Vss inside the semiconductor circuit, the energy band of the base region is further lowered and the PN diode is turned off, resulting in blocking the current flow. However, as shown in FIG. 3C, if the base voltage becomes lower than the boosted voltage Vpp, the PN diode is turned on and, thus, there occurs the current flow from the emitter to the base.
In case of the CMOS inverter in FIG. 1, since a base of the PNP type bipolar junction transistor 108 is connected to a collector of the NPN type bipolar junction transistor 109 and a base of the NPN type bipolar junction transistor 109 is attached to a collector of the PNP type bipolar junction transistor, both of the PNP type and the NPN type bipolar junction transistors 108 and 109 are turned on by their interaction and, thus, there occurs the current flow from the supply voltage node Vdd, i.e., the source of the PMOS transistor, to the ground voltage node Vss, i.e., the source of the NMOS transistor.
Meanwhile, since the afore-mentioned latch up can occur within a DRAM device, it can be figured out in detail hereinafter.
FIG. 4 represents a block diagram of a core area in a DRAM device. As described in the drawing, the core area includes dynamic type memory cells 111, each cell consisting of one transistor and one capacitor, a pair of bit lines BL and /BL for reading and writing data of the cells 111, a precharging unit 112 for precharging the bit line pair, a sense amplifier 113, connected to the bit line pair, for amplifying electric potential difference of the bit line pair, and a sense amplifier driver 114 for providing driving signals RTO and SB to the sense amplifier 113. An equalization signal BLEQ is coupled to the bit line precharging unit 112 and an equalizer in the sense amplifier driver 114.
FIG. 5 illustrates a CMOS inverter for producing a conventional equalization signal bleq and FIG. 6 shows a circuit for precharging and equalizing a conventional data line lio or gio.
As shown in FIG. 5, in the CMOS inverter for generating the conventional equalization signal bleq, a PMOS transistor 121 uses a supply voltage VDD as its source voltage and a boosted voltage VPP as its bulk bias. On the other hand, an NMOS transistor 122 uses a ground voltage VSS as its source voltage and a reduced voltage VBB as its bulk bias. In case the boosted voltage VPP and the reduced voltage VBB are unstable, since a parasitic PNP type bipolar junction transistor of the PMOS transistor 121 and a parasitic NPN type bipolar junction transistor of the NMOS transistor 122 are in gear and interact, excess current flows from VDD to VSS and, as a result, there occurs the latch up phenomenon inducing the destruction and malfunction of the device.
In the circuit for precharging and equalizing the conventional data line lio or gio described in FIG. 6, a core voltage VCORE that is lower than the supply voltage VDD used in peripheral circuits of a semiconductor memory device is used as a source voltage of PMOS transistors 123, 125, 127 and 128. The core voltage VCORE is derived from the supply voltage VDD.
An operational principle of a data line precharging/equalizing circuit is as follows. If a data line driving unit 131 is coupled with an input signal in of a high level and an inverted input signal inb of a low level, the data line lio and the inverted data line liob are driven to the ground voltage level VSS and the core voltage level VCORE, respectively. On the other hand, if the data line driving unit 131 is provided with the input signal in of a low level and the inverted input signal inb of a high level, the data line lio and the inverted data line liob are driven to the core voltage level VCORE and the ground voltage level VSS, respectively.
When precharging and equalizing the data line pair lio and liob, the data line driving unit 131 does not perform the driving operation in response to the input signals in and inb of a low level coupled thereto, which make the transistors 123 to 126 of the data line driving unit 131 turned off. After then, a precharging/equalizing unit 132 is activated in response to a data line equalizing control signal lio_eq having a low level. The data line pair lio and liob are precharged with the core voltage VCORE by the operation of the PMOS transistors 127 and 128 of the precharging/equalizing unit 132 and they are equalized to an identical level by the operation of a PMOS transistor 129.
Namely, if the equalizing control signal lio_eq having a low level is inputted, the data line precharging transistors 127 and 128 are turned on to precharge the data line pair with the core voltage VCORE and the equalizing transistor 129 is turned on to equalize the data line pair lio and liob (or gio and giob) to the identical level.
The principle in which the latch up occurs in the data line equalizing circuit of FIG. 6 is identical to that of the CMOS inverter of FIG. 5 and, thus, the repeated explanation will be omitted. Regions in which the latch up occurs are as follows. Firstly, the latch up occurs at the PMOS transistor 123 and the NMOS transistor 124 for precharging the inverted data line liob (or giob) of the data line driving unit 131. Secondly, the latch up occurs at the PMOS transistor 125 and the NMOS transistor 126 for precharging the data line lio (or gio) of the data line driving unit 131. Lastly, the latch up occurs since a closed loop is made by the PMOS transistor 127 in the data line precharging/equalizing unit 132 and the NMOS transistor 124 for precharging the inverted data line liob (or giob). Likewise, the latch up occurs since a closed loop is made between the PMOS transistor 128 in the data line precharging/equalizing unit 132 and the NMOS transistor 126 for precharging the data line lio (or gio) in the data line driving unit 131.
As shown in FIGS. 5 and 6, in the structure of just using the supply voltage VDD and the core voltage VCORE, when the boosted voltage VPP and the reduced voltage VBB are unstable, wherein the boosted voltage VPP is obtained by boosting the supply voltage VDD used as the bulk bias of the PMOS transistor and the NMOS transistor as much as the minimum threshold voltage Vth and the reduced voltage VBB is made by reducing the ground voltage VSS as much as the minimum threshold voltage Vth, the latch up phenomenon inducing the destruction and malfunction of the device occurs by excess current flowing from the supply voltage VDD and the core voltage VCORE to the ground voltage VSS, wherein the excess current is induced by the interaction of the PNP type bipolar junction transistor in the PMOS transistor region and the NPN type bipolar junction transistor in the NMOS transistor region.
Among the conventional technology of preventing the latch up, there is a method of reducing a gain of the parasitic bipolar junction transistor. This method decreases the current gain of the parasitic bipolar junction transistor by dropping a bias voltage between the base and the emitter through reducing parasitic resistance. As methods for reducing the parasitic resistance, there are a method of reducing substrate resistance by using an epitaxial layer and that of reducing well resistance by using a retrograde well or increasing well doping. As another method, there is a method of forming pick-up to have a sufficient distance when performing layout. However, these methods are not effective since an area increases and they are not applicable since it is required to change parameters of manufacturing and a device.